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AMD engineers used Mentor, a Siemens business's TSMC certified Calibre nmDRC software platform to achieve physical verification of their largest 7nm chip design, the Radeon Instinct Vega20, in about 10 hours.The verification process was performed on Microsoft Azure cloud platform using HB series virtual machines driven by AMD EPYC processor.
Although AMD has a staggering 13.2 billion transistors in its chip design, its TSMC 7nm Calibre design suite, which runs in Azure, enabled AMD to complete two validations in 19 hours, significantly reducing the overall turnaround time for physical validation.In addition, AMD has expanded Calibre nmDRC to 4,140 cores on 69 HB virtual machines, enabling engineers to balance tight deadlines with demanding resource requirements and other costs.
Mentor's new expansion and memory consumption enhancements for Calibre software customers set the stage for this milestone with Azure.These features not only help customers reduce memory requirements and associated costs, but can also help significantly reduce physical validation time when using traditional internal private "fog" or cloud-based configurations.Mentor works with TSMC and AMD to implement these enhancements and validate the results using the latest version of Calibre nmDRC.
"AMD's work in designing cutting-edge semiconductors requires speed and execution quality.As a result, having two validations in the cloud in one day is critical to getting future designs to market, "said Daniel Bounds, senior director of AMD's data center products division.
Calibre's latest enhancements enable multiple customers to reduce the memory requirements of their cloud and traditional configurations by as much as 50 percent while performing full chip validation of the latest 7nm design.Memory requirements are a key cost driver for public cloud and fog computing, and Calibre has been an industry leader in efficient use of memory.
"Mentor growing our software solutions, no matter where customers choose physical verification, can help them faster time-to-market," Mentor IC EDA, executive vice President Joe Sawicki said, "we are very glad to further cooperation with TSMC, by offering more options to help run together on a third party cloud customers make full use of TSMC technology and Mentor software platform, enabling them to new technology to produce faster by TSMC integrated circuit."
TSMC recently certified Mentor's Calibre tool, which runs on TSMC's 5nm FinFET process node through cloud processes hosted by Microsoft Azure and other leading cloud service providers.Mentor was also invited to join TSMC's OIP cloud alliance, which is dedicated to expanding TSMC's OIP ecosystem with new cloud-ready design solutions and helping customers unlock the innovation potential of TSMC process nodes.
"This latest achievements once again proved that the Mentor of TSMC OIP the value of the ecosystem," TSMC design infrastructure management department senior director Suk Lee said, "this cooperation has achieved satisfactory results, we succeeded in TSMC technology and design implementation and Mentor design platform and Microsoft Azure cloud services are united in wedlock, it is a significant milestone."
